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| PI6C182B Precision 1-10 Clock Buffer Features * Low noise non-inverting 1-10 buffer * Supports frequency up to 140 MHz * Supports up to four SDRAM DIMMs * Low skew (<200ps) between any two output clocks * I2C Serial Configuration interface * Multiple VDD, VSS pins for noise reduction * 3.3V power supply voltage * Separate Hi-Z state pin for testing * Industrial Temperature Range (-40C to +85C) * Packaging: (Pb-free & Green available) --28-pin SSOP (H) Description The PI6C182B is a high-speed low-noise 1-10 non-inverting buffer designed for SDRAM clock buffer applications and supports higher frequencies up to 140 MHz. At power up all SDRAM output are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the 10 output drivers. The output enable (OE) pin may be pulled low to Hi-Z state on all outputs. Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips. Diagram SDRAM0 Pin Configuration VDD0 SDRAM1 BUF_IN SDRAM2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD5 SDRAM7 SDRAM0 SDRAM1 VSS0 VDD1 SDRAM2 SDRAM3 SDRAM6 VSS5 VDD4 SDRAM5 SDRAM4 VSS4 OE VDD3 SDRAM9 VSS3 VSSIIC SCLOCK SDRAM3 VSS1 BUF_IN SDRAM17 OE SDATA SCLOCK I2C I/O VDD2 SDRAM8 VSS2 VDDIIC SDATA 1 PS8465C 09/07/05 PI6C182B Precision 1-10 Clock Buffer Pin Description Pin 2, 3, 6, 7 22, 23, 26, 27 11, 18 9 20 14 15 1, 5, 10, 19, 24, 28 4, 8, 12, 17, 21, 25 13 16 Symbol SDRAM[0-3] SDRAM[4-7] SDRAM[8-9] BUF_IN OE SDATA SCLOCK VDD[0-5] VSS[0-5] VDDIIC VSSIIC Type O O O I I I/O I/O Power Ground Power Ground Qty 4 4 2 1 1 1 1 6 6 1 1 SDRAM Byte 0 clock output SDRAM Byte 1 clock output SDRAM Byte 2 clock output Input for 1-20 buffer Hi-Z states all outputs when held LOW. Has a >100k internal pull-up resistor. Data pin for I2C curcuitry. Has a >100k internal pull-up resistor. Clock pin I2C circuitry. Has a >100k internal pull-up resistor. 3.3V power supply for SDRAM buffer Ground for SDRAM buffers 3.3V power supply for I2C circuitry Ground for I2C circuitry Description OE Functionality OE 0 1 Notes: 1. Used for test purposes only 2. Buffers are non-inverting SDRAM[0-9] Hi-Z BUF_IN Notes 1 2 Serial Configuration Map Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit 7 6 5 4 3 A2 0 A1 0 A0 1 R/W 0 2 1 0 7 6 3 2 Pin Description NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) I2C Address Assignment A6 1 A5 1 A4 0 A3 1 Note: 1. Inactive means outputs are held LOW and are disabled from switching 2 PS8465C 09/07/05 PI6C182B Precision 1-10 Clock Buffer 2-Wire I2C Control The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C182B is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every byte put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLOCK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLOCK is HIGH indicates a "start" condition. A LOW to HIGH transition on SDATA while SCLOCK is HIGH is a "stop" condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device's own address is detected, PI6C182B generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. "Command Code" byte 2. "Byte Count" byte. Although the data bits on these two bytes are "don't care," they must be sent and acknowledged. Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit 7 6 5 4 3 2 1 0 Pin 27 26 23 22 Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) Byte2: Optional Register for Possible Future Requirements (1 = enable, 0 = disable) Bit 7 6 5 4 3 2 1 0 Pin 18 11 Description SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature............................................................-65C to +150C Ambient Temperature with Power Applied...........................-40C to +85C 3.3V Supply Voltage to Ground Potential ..............................-0.5V to +4.6V DC Input Voltage....................................................................-0.5V to +4.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply Current (VDD = +3.465V, CLOAD = Max.) Symbol IDD IDD IDD IDD Supply Current Parameter Test Condidtion BUF_IN = 0 MHz BUF_IN = 66.66 MHz BUF_IN = 100.00 MHz BUF_IN = 133.00 MHz Min. Typ. Max. 2 180 240 360 mA Units 3 PS8465C 09/07/05 PI6C182B Precision 1-10 Clock Buffer DC Operating Specifications (VDD = +3.3V 5%, TA = - 40C to + 85C) Symbol Input Voltage VIH VIL IIL Input High voltage Input Low voltage Input leakage current 0 < VIN < VDD VDD 2.0 VSS -0.3 -5 VDD +0.3 0.8 5 mA V Parameter Test Conditions Min. Typ. Max. Units VDD [0-9] = 3.3V 5% VOH VOL COUT CIN LPIN TA Output High voltage Output Low voltage Output pin capacitance Input pin capacitance Pin Inductance Ambient Temperature No Airflow 0 IOH = -1mA IOL = 1mA 6 5 7 70 nH C 2.4 0.4 pF V SDRAM Clock Buffer Operating Specification Symbol IOHMIN IOHMAX IOLMIN IOLMAX Parameter Pull-up current Pull-up current Pull-down current Pull-down current Test Conditions VOUT = 2.0V VOUT = 3.135V VOUT = 1.0V VOUT = 0.4V 54 53 Min. -54 -46 mA Typ. Max. Units AC Timing Symbol tSDRISE tSDFALL tPLH tPHL tPZL, tPZH tPLZ, tPHZ Duty Cycle tSDSKW Parameter SDRAM CLK rise time SDRAM CLK fall time SDRAM Buffer LH prop delay SDRAM Buffer HL prop delay SDRAM Buffer Enable Measured at 1.5V SDRAM Output-to-Output skew delay(1) SDRAM Buffer DIsable delay(1) 66 MHz Min. 1.5 1.5 1.0 1.0 1.0 1.0 45 Max. 4.0 4.0 5.0 5.0 8.0 8.0 55 250 100 MHz Min. 1.5 1.5 1.0 1.0 1.0 1.0 45 Max. 4.0 4.0 5.0 5.0 8.0 8.0 55 250 133MHz Min. 1.5 1.5 1.0 1.0 1.0 1.0 45 Max. 4.0 4.0 5.0 5.0 8.0 8.0 55 200 % ps ns Units V/ns Note: 1. This Parameter specified at 5 MHz input frequency. 4 PS8465C 09/07/05 PI6C182B Precision 1-10 Clock Buffer Output Buffer Test Point Test Load tSDKP tSDKH 3.3V Clocking Interface (TTL) 2.4 1.5 0.4 tSDKL tSDRISE tSDFALL Input Waveform tplh Output Waveform 1.5V 1.5V tphl 1.5V 1.5V Figure 1. Clock Waveforms Minimum and Maximum Expected Capacitive Loads Clock SDRAM Min. 15 Max. 20 Units pF Notes SDRAM DIMM Specificaion Design Guidelines to Reduce EMI 1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of "vias" of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors. Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel. 5 PS8465C 09/07/05 PI6C182B Precision 1-10 Clock Buffer PCB Layout Suggestion C1 VDD 1 2 3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS VSS VDD VSS VSS VDD VDD C7 Ferrite Bead VCC C8 C2 VSS VDD 4 5 6 7 C6 22uF VSS 8 9 C3 VDD C5 10 11 Via to GND Plane Via to VDD Plane Void in Power Plane C4 VSS VDD 12 13 14 Note: 1. This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. 2. As a general rule, C1-C7 should be placed as close as possible to their respective VDD. 3. Recommended capacitor values: C1-C7 = 0.1F, ceramic C8 = 22F PI6C182B 100/66 MHz Clock from Chipset SDRAM 10 RS CL SDRAM DIMM Spec. Figure 2. Design Guidelines 6 PS8465C 09/07/05 PI6C182B Precision 1-10 Clock Buffer Packaging Mechanical: 28-Pin SSOP (H) Ordering Information Ordering Code PI6C182BH PI6C182BHE Package Code H H 28-pin SSOP Pb-free & Green, 28-pin SSOP Package Type Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 7 PS8465C 09/07/05 |
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